Memory devices including SRAM's, DRAM's and ROM's are widely used in electronic circuits to store data in the form of logic bits which can be accessed by using a memory address. Generally, a memory address is provided to a memory device, and the memory device executes a memory cycle to provide data from or store data to the location in the memory device associated with the memory address.
Memory devices are implemented according to various architectures. Memory devices may include a memory array containing a large number of memory cells where each memory cell can be set to one of two data states storing one bit of information. The memory cells often are arranged in rows and columns, thus each memory cell can be referenced by a unique memory address which includes a row address and a column address. Generally, a row address selects a word line that enables access of each memory cell in that row to associated column or bit lines, where the bit lines may be in pairs to transmit differential signals. Large memories may be divided into blocks such that the row address selects a global word line that is selectively connected to block word lines in response to the block address. The block address may be included in the general term of column address, since it is part of the address that selects a particular column.
Memory devices commonly operate in a read mode and a write mode, thus memory devices execute memory read cycles and memory write cycles. In many memory devices, the data states of every memory cell in the row specified by the row address are accessed during a memory read cycle. These data states are then multiplexed according to the column address to provide an output which represents the data states of the memory cells corresponding to the memory address. The number of memory cells for which the data state is output in one access depends on the organization of the given memory. Typical organizations are x1, x4, or x8. The output from a memory array prior to multiplexing represents all or a subset of the memory cells corresponding to the row address. A memory write cycle usually operates in a manner similar to a memory read cycle with the data state of the memory cell corresponding to the memory address being set according to a data value provided to the memory device. Memory devices can be designed such that read and write cycles can read from or store to one or more memory cells.
In some memory devices, address transition detection is used to detect changes in the memory address and to initiate a full memory cycle only when the memory address changes sufficiently. A low power access mode can be implemented by distinguishing row address changes from column address changes and initiating a memory array access only when the row address changes. One implementation of such a low power access mode is to latch the outputs of the memory array representing the data states of memory cells corresponding to the row address. A change in the memory address that only includes a change in the column address then can be handled by accessing the latched data states rather than accessing the memory array. This low power access mode saves power by preventing the memory device from precharging the memory array and decoding the full memory address for memory read cycles during which the row address does not change.
While latching the data at each column allows this low power access mode, it may be difficult to layout a latch to fit in the pitch of a column. Also, in large memories, the multiplexing of data from the columns to the output may be done in several stages. The driving and sensing of data through the plurality of stages in the multiplexer further consumes power even in such a low power access mode. This particularly may be true if differential signals are used in multiplexing to reduce access time.
The sensing of the outputs of the memory array consumes power and can cause a power consumption problem in memory devices with large memory arrays. Sensing the outputs of the memory array prior to multiplexing the outputs can require the driving of column lines and activating sense amplifiers equal to the width of the memory array. For example, a 64-bit RAM having 256 rows and 256 columns would require 256 sense amplifiers to sense the data states of every memory cell in one row. Even in a memory access cycle in which the row address does not change, the 256 columns must be driven and 256 sense amplifiers activated consuming power. Further, if the outputs of the memory array are implemented as differential signals and are multiplexed, sense amplifiers must be paired with each input to the multiplexer and also consume power. Driving these devices causes power consumption even during a low power access mode when the row address does not change. This power consumption is a problem because it is desirable for a memory device to consume as little power as possible.